Semiconductor Micro-Nano Structure Analysis: Principles, Methods, and Applications

Semiconductor micro-nano structure analysis is a critical characterization discipline that enables precise measurement and evaluation of structural features in semiconductor materials and devices at micrometer and nanometer scales. As device geometries continue to shrink below 10 nanometers, advanced analytical techniques such as electron microscopy, X-ray diffraction, and atomic force microscopy have become indispensable for process development, quality assurance, and failure analysis. This comprehensive guide explores the testing samples, items, methods, and applications of semiconductor micro-nano structure analysis in modern electronics manufacturing.

Technical Overview

Semiconductor micro-nano structure analysis refers to the systematic characterization of structural, morphological, and dimensional features of semiconductor materials and devices at length scales ranging from several micrometers down to the atomic level. As integrated circuit technology advances toward sub-10 nm process nodes and wide-bandgap semiconductors such as silicon carbide (SiC) and gallium nitride (GaN) gain widespread adoption, the ability to accurately observe, measure, and interpret micro- and nano-scale structures has become fundamental to device performance, reliability, and yield.

The discipline encompasses several interconnected domains, including critical dimension (CD) metrology, thin film characterization, crystal defect analysis, interface and junction profiling, and surface topography evaluation. Structural variations at the nanoscale—such as gate line edge roughness, epitaxial layer defects, trench sidewall angles, and grain boundary anomalies—directly influence electrical characteristics, leakage currents, breakdown voltages, and long-term device reliability. Consequently, micro-nano structure analysis serves as an essential feedback loop in semiconductor research, development, and manufacturing.

Modern analysis relies on a complementary suite of instrumentation, combining high-resolution imaging techniques (scanning electron microscopy, transmission electron microscopy), surface probing methods (atomic force microscopy, profilometry), diffraction-based techniques (X-ray diffraction and reflectivity), and chemical profiling tools (secondary ion mass spectrometry, energy-dispersive spectroscopy). Accredited third-party laboratories typically perform these analyses in accordance with international standards published by organizations such as ISO, IEC, ASTM International, SEMI, and JEDEC, ensuring measurement traceability and cross-facility comparability.

Testing Samples

Silicon Wafers and Substrates

Bare and patterned silicon wafers, including CZ-grown and FZ-grown substrates, silicon-on-insulator (SOI) wafers, and engineered substrates. Analysis focuses on surface roughness, crystallographic defects, oxide thickness uniformity, and wafer-level dimensional metrology.

Epitaxial Layers and Heterostructures

Silicon epitaxial layers, SiC epilayers for power devices, III-V compound heterostructures (GaN-on-Si, GaAs/AlGaAs, InGaAs/InP), and quantum well structures. Key measurements include layer thickness, interface abruptness, mismatch strain, and defect density.

Patterned IC Structures

Fabricated device structures such as gate stacks, fin structures, nanosheet channels, shallow trench isolation (STI), damascene interconnects, through-silicon vias (TSVs), and contact holes. These samples require cross-sectional analysis of critical dimensions, sidewall profiles, and overlay fidelity.

MEMS and Micro-Nano Devices

Micro-electromechanical systems (MEMS) including accelerometers, resonators, micro-mirrors, and pressure sensors, as well as nanowires, nanotubes, quantum dots, photonic crystals, and other emerging nanostructures used in sensors, photonics, and quantum devices.

Thin Films and Coatings

Dielectric films (SiO2, Si3N4, high-k dielectrics), metal films (Al, Cu, W, TiN), barrier layers, photoresist coatings, and hard mask materials deposited by CVD, PVD, ALD, or spin-on processes.

Discrete Power and Optoelectronic Devices

Power MOSFETs, IGBTs, SiC Schottky diodes, GaN HEMTs, LEDs, and laser diodes requiring analysis of junction depths, termination structures, defect distribution, and die-level structural integrity.

Testing Items

Semiconductor micro-nano structure analysis covers a broad portfolio of measurable parameters. Typical testing items include:

• Critical dimension (CD) measurement: line width, trench width, contact/via diameter, hole diameter, and pitch
• Line edge roughness (LER) and line width roughness (LWR) quantification
• Thin film thickness, refractive index, and extinction coefficient determination
• Film stack analysis: multilayer thickness, interface roughness, and interlayer mixing
• Surface roughness parameters (Ra, RMS, Rz) and three-dimensional topography mapping
• Sidewall angle, profile shape, and etch depth evaluation
• Crystal defect characterization: dislocations, stacking faults, threading defects, micropipes, and voids
• Grain size distribution, grain orientation, and texture analysis in polycrystalline films
• Epitaxial layer thickness, doping concentration depth profiles, and junction depth measurement
• Residual stress and strain analysis in films and device structures
• Crystal quality metrics: rocking curve FWHM, lattice constant, crystallinity, and mosaicity
• Porosity and density characterization of low-k dielectrics
• Elemental composition and impurity distribution mapping
• Particle and contamination inspection, plus defect review and classification
• Via and TSV dimensional integrity, fill quality, and void detection

Testing Methods

Scanning Electron Microscopy (SEM)

Field-emission SEM provides high-resolution imaging of surface topography and cross-sections, enabling critical dimension measurement, defect review, and surface morphology evaluation. Complementary techniques such as stereo-SEM reconstruction allow non-destructive CD metrology. Test methods are guided by standards such as ASTM E2809 and SEMI metrology specifications.

Transmission Electron Microscopy (TEM)

TEM and scanning TEM (STEM) deliver atomic-resolution imaging of internal structures, interfaces, and crystal defects. High-resolution TEM (HRTEM) resolves lattice fringes for epitaxial quality assessment, while convergent beam electron diffraction (CBED) and nano-beam diffraction determine local strain. Specimens are prepared as electron-transparent lamellae, typically by focused ion beam (FIB) milling.

Focused Ion Beam (FIB) Sectioning

FIB systems precisely mill cross-sections at targeted sites, exposing buried structures for subsequent SEM or TEM examination. FIB-SEM dual-beam platforms also enable three-dimensional tomography through sequential slice-and-image workflows, providing volumetric reconstructions of interconnects, vias, and voids.

Atomic Force Microscopy (AFM)

AFM provides nanometer-scale three-dimensional topography measurement with sub-nanometer vertical resolution. It is used for surface roughness quantification, step height measurement, CD AFM profiling of deep trench structures, and nanomechanical property mapping. Guidelines from ISO 25178 govern areal surface texture parameters.

X-ray Diffraction (XRD) and X-ray Reflectivity (XRR)

High-resolution XRD (HRXRD) measures lattice constants, strain, composition, and crystalline quality through rocking curves and reciprocal space mapping. XRR determines film thickness, density, and interface roughness for multilayer stacks with sub-nanometer precision. Both methods are non-destructive and aligned with standards such as ASTM E1676-related practices and SEMI material specifications.

Secondary Ion Mass Spectrometry (SIMS)

SIMS delivers depth profiling of dopant and impurity concentrations with detection limits down to parts per billion, supporting junction depth measurement, doping profile verification, and contamination investigation. Dynamic SIMS provides depth profiling, while TOF-SIMS enables surface and interface molecular analysis.

Energy-Dispersive X-ray Spectroscopy (EDS) and Electron Energy Loss Spectroscopy (EELS)

Integrated with electron microscopes, EDS provides elemental composition mapping and line scans across cross-sections, while EELS offers nanoscale chemical state and thickness information, particularly for light elements and fine interfaces.

Spectroscopic Ellipsometry and Optical Profilometry

Spectroscopic ellipsometry non-destructively measures film thickness and optical constants across wafer surfaces. White-light interferometry and confocal optical profilometry provide rapid large-area topography and step height measurements for MEMS and wafer-level structures.

Electron Backscatter Diffraction (EBSD)

EBSD maps crystallographic orientation, grain boundaries, and local strain in polycrystalline metal interconnects and thin films, supporting reliability studies of electromigration and stress voiding.

Raman Spectroscopy and Cathodoluminescence

Raman spectroscopy assesses crystal quality, stress states, and phase composition in materials such as SiC, GaN, and graphene. Cathodoluminescence imaging reveals defect-related luminescence distributions in optoelectronic structures.

Applications

Advanced Node Process Development

Micro-nano structure analysis guides lithography, etch, and deposition process optimization at advanced technology nodes by quantifying CD uniformity, profile fidelity, LER, and film stack integrity, directly supporting yield ramp and process window definition.

Power Semiconductor Manufacturing

For SiC and GaN power devices, defect characterization (micropipes, basal plane dislocations, threading dislocations), epilayer thickness verification, and termination structure analysis are essential for achieving target breakdown voltage, reducing leakage, and ensuring long-term reliability in automotive and industrial applications per AEC-Q101 and related qualification frameworks.

Failure Analysis and Reliability Engineering

Cross-sectional microscopy, FIB sectioning, and elemental mapping locate structural root causes of electrical failures, including interconnect voiding, dielectric breakdown sites, delamination, and doping anomalies, supporting corrective action and reliability improvement.

MEMS and Sensor Development

Dimensional metrology of released structures, deep reactive ion etch (DRIE) profiles, and sacrificial layer removal completeness verifies device geometry against design targets, which governs resonant frequency, sensitivity, and mechanical reliability.

Incoming Material Qualification and Quality Control

Wafer suppliers and device manufacturers use standardized structural analysis to qualify incoming substrates, epilayers, and photomask blanks, ensuring supply chain quality through accredited third-party laboratories operating under ISO/IEC 17025 management systems.

Emerging Device and Material Research

Research into nanowire transistors, 2D materials, quantum dots, photonic integrated circuits, and advanced packaging (hybrid bonding, chiplets) relies on atomic-resolution structural analysis to correlate structure with electrical and optical performance.

Intellectual Property and Litigation Support

Reverse engineering, structural benchmarking, and process attribution analyses support patent investigations and competitive technical assessments, requiring defensible, standards-based measurement documentation.

FAQ

What resolution can semiconductor micro-nano structure analysis achieve?

Imaging resolution depends on the technique: field-emission SEM typically achieves 1–2 nm, TEM reaches sub-angstrom resolution on modern aberration-corrected instruments, and AFM provides sub-nanometer vertical resolution. Dimensional measurement uncertainty is typically in the range of a few percent for CDs and better than 0.1 nm for film thickness by XRR or ellipsometry.

Is cross-sectional analysis destructive?

Cross-sectioning by cleaving, mechanical polishing, or FIB milling is locally destructive to the sample. However, techniques such as SEM top-down imaging, XRD/XRR, ellipsometry, AFM, and Raman spectroscopy are non-destructive and can be applied to full wafers or finished devices.

How is defect density in SiC epilayers measured?

Defect density is typically quantified by combining non-destructive surface inspection (optical and photoluminescence-based mapping) with destructive cross-sectional TEM for detailed dislocation identification. Results are reported as defects per square centimeter, categorized by defect type such as micropipes, threading screw dislocations, and basal plane dislocations, in line with SEMI substrate specifications.

What is the difference between CD-SEM and CD-AFM?

CD-SEM offers fast, high-throughput top-down critical dimension measurement using electron beam imaging with model-based library analysis, making it suitable for in-line process monitoring. CD-AFM physically probes structures with a flared tip, providing true three-dimensional profiles including sidewall angles and depths, but with lower throughput.

Which standards govern these analyses?

Relevant standards and guides are published by ISO (e.g., ISO 25178 for areal surface texture), IEC (semiconductor device test methodologies), ASTM International (electron microscopy and X-ray methods), SEMI (wafer and metrology specifications), JEDEC (device reliability test methods), and GB standards for regional compliance. Accredited third-party laboratories typically align their procedures with these frameworks.

How should samples be prepared and submitted for analysis?

Samples should be cleaned, packaged in particle-free containers, and accompanied by design layout information identifying regions of interest. For TEM, lamella extraction is generally performed on-site at the laboratory. For SIMS depth profiling, flat unpatterned monitor wafers or dedicated test structures yield the most accurate quantitative results.

Can analysis be performed on finished packaged devices?

Yes. Decapsulation, delidding, and parallel polishing or FIB techniques expose internal structures of packaged devices, enabling die-level structural analysis, interconnect inspection, and failure site localization without destroying critical evidence.